In recent years, RF systems have been used as means for communicating information between devices in portable electronic devices, electric home appliances, peripheral devices for personal computers, and the like. Wireless systems used in these electronic devices are fabricated in semiconductor integrated circuits to reduce size and weight and to lower price. Generally, an RF system requires a filter which has an abrupt cut-off frequency in order to separate a particular frequency component. However, since elements used in semiconductor integrated circuits suffer from substantial variability in manufacturing, it has been difficult to accomplish a filter circuit which has an abrupt cut-off frequency. Accordingly, a Gm-C filter composed of a transconductance amplifier [hereinafter called “OTA” (Operational Transconductance Amplifier) and a capacitance has been used.]
FIG. 1 is a diagram showing the basic configuration of a transconductance amplifier (hereinafter called “OTA” (Operational Transconductance Amplifier).
As illustrated, the OTA is an element for generating currents GmVin/2, −GmVin/2 which are proportional to input voltage Vin, and ideally has infinite input impedance and output impedance.
In this event, proportion coefficient Gm is a parameter called mutual conductance, and an OTA applied to a filter and the like is configured to have the ability to control the mutual conductance with a signal from the outside.
FIG. 2 is a circuit diagram showing a specific configuration of an OTA which is controlled mutual conductance Gm, for example, a degenerated differential OTA presented in Bran Nauta, “Analog CMOS Filters for Very High Frequencies”, Kluwer Academic Publishers, 1993, pp. 87-88.
Current sources 404, 405, 406, 407 each apply the same current value. Also, a resistive component of variable resistive element 403 connected to sources of input transistors 401, 402 varies in resistance in response to mutual conductance control signal 408 applied from the outside.
When input transistors 401, 402 have large transconductance, a current of ΔV/R/2 appears at the output, where R represents a resistive component of variable resistive element 403. Here, ΔV represents a voltage of a differential component of a voltage signal applied to the input. Therefore, arbitrary mutual conductance Gm can be accomplished by controlling the resistance of variable resistive element 403 with control signal 408. This configuration of an input stage is generally called a total differential input stage.
With the miniaturization of processes in recent years, lower voltages have been required for power supplies. In particular, when a source voltage is equal to or lower than one volt, limitations are imposed on the number of vertically stacked stages of transistors which can be used between the power supply and GND, thus making it impossible to use conventional circuit configurations. In the circuit configuration shown in FIG. 2, at least one or more transistors are required in the current source, three stages of transistors are used between the power supply and GND when they are vertically stacked. A transistor generally requires a drain-source voltage of approximately 200 mV when it operates in a saturation region, so that when transistors are vertically stacked in three stages, 600 mV is required irrespective of the magnitude of the signal. Accordingly, when the source voltage is one volt, only 400 mV is available for a signal amplitude, giving rise to a problem of the inability to provide a sufficient amplitude.
FIG. 3 includes diagrams showing the configuration of a pseudo-differential input type OTA disclosed in Ahmed Nader Mohieldin, “Nonlinear Effects in Pseudo Differential OTAs with CMFB”, IEEE Transactions on Circuits and Systems, Vol. 50, No. 10, October 2003, pp. 762-769, where FIG. 3a is a circuit diagram, and FIG. 3b is an equivalent circuit diagram of an output stage.
In FIG. 3a, sources of p-moss transistors M2A, M2B, M02A, M02B are commonly connected to a power supply, while source of n-moss transistors M1A, M1B, M01A, M01B are commonly grounded. Each drain of p-mos transistor M2A, M2B, M02A, M02B is connected to each drain of n-moss transistors M1A, M1B, M01A, M01B, while gates of p-moss transistors M2A, M02A are connected to a drain of p-moss transistor M02A, and gates of p-mos transistors M2B, M02B are connected to a drain of p-mos transistor M02B, to form a current mirror circuit. Each gate of n-moss transistor M1A, M01A is connected in common, and each gate of n-mos transistors M1B, M01B is connected in common to define an input part of gate signals Va, Vb. Output current Iout1 is generated from the drains of transistors M1A, M2A, while output current Iout2 is generated from the drains of transistors M1B, M2B.
In the circuit configured as described above, transistors M1A, M1B are input transistors, transistors M01A, M01B convert common-mode components of a signal from a voltage to a current, and a current proportional to the common-mode components is supplied to transistors M1A, M1B by the current mirror circuit composed of transistors M02A, M02B and transistors M2A, M2B.
A current flowing through a current source has a current value one half of a current value proportional to the common-mode components of the signal generated by transistors M01A, M01B.
Generally, drain current ID of a MOSFET is represented by:ID=½μCax[W/L](VGS−VT)2 
When the drain current of a transistor applied with a gate-source voltage Va is I1, and the drain current of a transistor applied with a gate-source voltage Va is I2, where the size (W/L) of each transistor is the same, I1, I2 can be represented in the following manner through simplification of the above equation:I1=k(Va−VT)2 I2=k(Vb−VT)2 
Here, when Vc=Va+Vb,I1−I2=k(Vc−2VT)(Va−Vb),and difference ΔI of the current is represented by:ΔI=Gm(Va−Vb)
As shown in this equation, difference ΔI of currents which flow through the two types of transistors has a value proportional to the difference between gate signals Va, Vb applied to their gates, thus permitting the transistors to act as an OTA.
The example shown in FIG. 3 will be described. Assuming that transistors M1A, M1B, M01A, M01B are equal in size to one another, and M2A, M2B, M02A, M02B are equal in size to one another, drain current I1 flows into transistors M1A, M01A applied with signal Va between the gate and source, while drain current I2 flows into transistors M1B, M01B applied with signal Vb between the gate and source, respectively. Since drain currents I1, I2 of M01A, M01B are mirrored by the current mirror circuit composed of M2A, M02A and M2B, M02B, a current of (I1+I2)/2 flows into the drains of transistors M2A and M2B, respectively. Here, since the drain currents of transistors M1A and M1B are I1, I2, respectively, currents of (I1−I2)/2, (I1−I2)/2 are output from the output stage of FIG. 3b. Thus, since the difference between I1 and I2 is output in proportion to the difference between gate signals Va, Vb, they act as an OTA. In this regard, in the exemplary OTA shown in FIG. 3, when the mutual conductance is changed from the outside, it can be controlled by controlling an common-mode bias voltage of an input signal.
FIG. 4 is a diagram showing a pseudo differential input type OTA shown in FIG. 3 in a functional block form. In FIG. 4, first voltage/current converting element 1701 and third voltage/current converting element 1703 correspond to transistors M1A, M1B, while second voltage/current converting element 1702 and fourth voltage/current converting element 1704, which form part of common-mode current generating part 1705, correspond to transistors M01A, M01. Current mirror circuit 1706, which corresponds to transistors M02A, M02B and transistors M2A, M2B, is a circuit for inverting the polarity of an input current to output a current which is proportional to the input current.
As described above, the output impedance of the OTA is ideally infinite. As such, in the circuits shown in FIGS. 1 to 3, an output DC bias overshoots to the power supply side or to the ground side, being incapable of acquiring a signal. Accordingly, a CMFB (Common Mode Feed Back) circuit is known for setting an output DC bias (see Non-Patent Document 2).
FIG. 5 includes diagrams showing the configuration of a CMFB circuit, where FIG. 5a is a block diagram conceptually showing the configuration of the CMFB circuit, FIG. 5b is a circuit diagram showing a specific configuration, and FIG. 5c is a block diagram showing an exemplary application of the CMFB circuit.
First, the operation of the CMFB circuit will be described with reference to FIG. 5a. Common-mode bias detecting circuit 703, which forms part of CMFB circuit 702, is applied with outputs VOUT+, VOUT− of OTA 701, and feeds an common-mode bias component of them back to OTA 701 as output bias control signal 704. In addition to output bias control signal 704, OTA 701 is applied with reference signal 705 as a control signal, such that OTA 701 compares output bias control signal 704 with reference signal 705 to control its output such that output bias control signal 704 provides a predetermined constant bias.
In this regard, while the CMFB circuit can refer to an common-mode bias detecting circuit provided externally to the OTA, as shown in FIG. 5a, the CMFB circuit includes circuits within the OTA for receiving the output bias control signal and reference signal for performing the comparison and feedback, in addition to the common-mode bias detecting circuit.
As shown in FIG. 5b, this conventional example comprises n-mos transistors M3A′, M3A, M03A, M2A, M3B′, M3B, M03B, M2B and p-mos transistors M04A′, M4A, M04A, M1A, M04B′, M4B, M04B, M1B.
Respective p-mos transistors M1A, M1B, M04A, M04B, M4A, M4B correspond to n-mos transistor M2A, M2B, M03A, M03B, M3A, M3B, and these corresponding transistors have a common drain, and are provided between the power supply and ground to form an OTA. P-mos transistors M1A, M1B and n-mos transistors M2A, M2B make up an input differential pair, and VIN+, VIN− are supplied to the gates of p-mos transistors M1A, M1B. Transistors M1A, M2A have their drains connected to the gates of transistors M2A, M03A, M3A, while transistors M1B, M2B have their drains connected to the gates of transistors M2B, M03B, M3B.
Each gate of p-mos transistors M1A, M1B, M04A, M04B, M4A, M4B is made common, serve as node VX (preceding stage), and is connected to the drains of transistors M04A, M04B. Transistors M3A, M3B, M4A, M4B make up an output stage of the OTA, where the drains of transistors M3A, M3B are used for an output node of VOUT+, while the drains of transistors M4A, M4B are used for an output node of VOUT−.
Transistors M3A′, M3B′, M4A′, M4B′ form part of the CMFB circuit, where transistor M3A′ which is supplied with reference signal VY at a gate has a source grounded, and has a drain connected to the drains of transistors M3A, M4A. Transistor M3B′ which is applied with reference signal VY at a gate has a source grounded, and has a drain connected to the drains of transistors M3B, M4B. Transistor M4A′, the gate of which serves as node VX (next stage), has a source connected to a power supply, and a drain connected to drains of transistors M3A, M4A. Transistor M4B′, whose gate serves as node VX (next stage), has a source connected to the power supply, and a drain connected to drains of transistors M3B, M4B.
In FIG. 5b, a circuit made up of transistors M1A, M1B, M2A, M2B is a circuit at an input stage for generating Va, Vb at the gates of transistors M2A, M2B, and is a circuit corresponding to a circuit for generating Va, Vb in the circuit diagram shown in FIG. 3a. Other parts corresponding to the circuit diagram of FIG. 3a are as follows.
Transistors M03A, M03B, M04A, M04B in FIG. 5b correspond to transistors M01, M02 in FIG. 3a, and transistors M3A, M3B, M4A, M4B correspond to transistors M1, M2 in FIG. 3a. Also, among the transistors shown in FIG. 5b, transistors M3A′, M3B′, M4A′, M4B′ which have no corresponding transistors in FIG. 3a form part of the CMFB circuit.
Next, the operation of the circuit shown in FIG. 5b will be described.
The operation of the OTA part in this conventional example is similar to the operation described with reference to FIG. 3a. As VIN+, VIN− are applied to input transistor pair M1A, M1B, Va, Vb are generated at the gates of transistors M03A, M03B, and are converted from voltage to current to remove a differential component at node VX (preceding stage). When OTAs are connected in series at two or more stages, for example, OTA1 and OTA2 are connected in series at two stages as shown in FIG. 5c, VX (preceding stage) of OTA2 is connected to node VX (next stage) of OTA1 which is provided at the preceding stage. In this conventional example, an common-mode bias component of the output signal of OTA1 appears at node VX (preceding stage) of OTA2. By returning this common-mode bias component to node VX (next stage) of OTA1, a negative feedback is applied to an output common-mode bias of OTA1. Also, in this event, by supplying reference signal VY to the gates of transistors M3A′, M3B′, the common-mode biases of outputs VOUT+, VOUT− are set at predetermined biases.
Non-Patent Document 1: Bran Nauta, “Analog CMOS Filters for Very High Frequencies”, Kluwer Academic Publishers, 1993, pp. 87-88
Non-Patent Document 2: Ahmed Nader Mohieldin, “Nonlinear Effects in Pseudo Differential OTAs with CMFB”, IEEE Transactions on Circuits and Systems, Vol. 50, No. 10, October 2003, pp. 762-769